NAND flash is a key technology for all systems. 3D techniques now control its cost and potential for future capacity increases.
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
Refreshing the IEEE 1687 IJTAG family for today’s designs
Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.
- Expert Insight Welcome to the part model era
- Expert Insight Shift left to tackle key O-RAN verification challenges
Putting it all together to accelerate 3D IC design
Learn how connectivity management solutions help you manage the multiple formats in which 3D IC components are delivered.
- Expert Insight A three-phase strategy to master the supply chain tsunami
- Expert Insight May the Cloud be with you
How to migrate SoC design to the cloud
Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no ‘one-size-fits-all’.
- Expert Insight Give the people what they want: toward making 3D IC mainstream
- Article Formal verification for SystemC/C++ designs
Keeping up with rapid innovation in cockpit domain controllers
Automotive cockpit design is being driven forward by prevailing trends in the wider market.
- Expert Insight Use digitalization to mitigate the automotive MCU shortage
- Expert Insight Implementing medical device security for optimal outcomes
View All Sponsors