Latest

Yield Loss

PID yield loss countered by path-based antenna verification

Plasma induced damage (PID) in gate oxide is a threat to MOSFET circuit yield and reliability. How can you effectively combat this issue?

Guides

  • NAND flash

    IP - Technologies

    NAND flash is a key technology for all systems. 3D techniques now control its cost and potential for future capacity increases.

  • Interconnect resistance

    EDA - Techniques

    A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.

  • Real-number or wreal modeling

    EDA - Techniques

    Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.

Expert Insights

Stephen Chavez

Mastering the art of PCB routing

Stephen Chavez is chairman of the Printed Circuit Engineering Association (PCEA) and a Senior Product Marketing Manager with Siemens EDA. He is an IPC Certified Master Instructor Trainer (MIT) for PCB design, an IPC Certified Advanced PCB Designer (CID+), and a Certified Printed Circuit Designer (CPCD). He is chairman of the Printed Circuit Engineering Association (PCEA).

Learn which routing techniques offer a PCB designer the best balance between automation and control by applying them in harmony.

Ron Press

How AI improves DFT, test and yield

Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.

Neel Natekar

Simplify and accelerate PV debug using default results data views

Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.

EDA

  1. Article The keys to ensuring IC quality

    How the latest DFT techniques pave the way for quality and success for today’s advanced designs.

  2. Article Want to improve your user experience? Adopt a UX maturity model
  3. Article BCI-ROM: a game-changer for electro-thermal design

PCB

  1. Matthew Welsh, Siemens DIS
    Expert Insight Welcome to the part model era

    Standards-based digital threads will revolutionize design through part models that deliver trust, traceability and context across components.

  2. Article Putting it all together to accelerate 3D IC design
  3. Expert Insight A three-phase strategy to master the supply chain tsunami

IP

  1. Jeff Wilson is a Product Management Director for DFM applications in the Calibre Design solutions organization at Siemens Digital Industries Software. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.
    Expert Insight Improved power management and faster time to market?

    We have the technology. Learn how to ‘shift left’ with Calibre DesignEnhancer and meet IR, EM and PPA objectives.

  2. Expert Insight How to migrate SoC design to the cloud
  3. Expert Insight Give the people what they want: toward making 3D IC mainstream

Embedded

  1. Jeff Hancock is a Senior Product Manager in the Embedded Platform Technology Business Unit of Mentor, A Siemens Business. He oversees the Nucleus and Mentor Embedded Hypervisor runtime product lines, as well as associated middleware and professional services.
    Expert Insight Keeping up with rapid innovation in cockpit domain controllers

    Automotive cockpit design is being driven forward by prevailing trends in the wider market.

  2. Expert Insight Use digitalization to mitigate the automotive MCU shortage
  3. Expert Insight Implementing medical device security for optimal outcomes

Briefing

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